1. Field of the Invention
The present invention relates to a boosting circuit, and more particularly to a boosting circuit applied to a semiconductor device which requires a voltage higher than a power supply voltage.
2. Description of the Related Art
In an internal circuit of a semiconductor device exemplified as DRAM (Dynamic Random Access Memory), there is a case that a voltage higher than a power supply voltage is needed. In this case, a boosting circuit is used for supplying the voltage higher than the power supply voltage to an internal circuit of the semiconductor device. As the examples that the boosting circuit is needed, there are a case (1) of applying the voltage higher than the power supply voltage to a word line and a case (2) of applying the voltage higher than the power supply voltage to an anti-fuse.
In the case (1) that the boosting circuit is applied to the DRAM, in order to accumulate charge in a memory cell, a high voltage must be applied to the word line. For this reason, the boosting circuit is included in the semiconductor device for supplying a voltage equal to or high than a power supply voltage VDD. The potential of the word line potential in the DRAM is determined by considering the voltage corresponding to the charge accumulated in the memory cell, and the threshold voltage Vt of the cell transistor. For example, in a device designed in accordance with a 0.13 μm design rule, it is approximately set to 4 V. In the case (2), the boosting circuit is used for anti-fuses of the semiconductor device. The anti-fuse is the fuse that can be electrically turned ON/OFF, differently from a fuse that is physically cut away by laser from outside and the like. As such an anti-fuse, a capacitive fuse is exemplified. In the capacitive fuse, in an initial state, a capacitor has electrically opened terminals. In this capacitive fuse, by giving the high electrical field between the terminals, it is possible to break down an insulating film (a capacitive film). Thus, the terminals can be switched to an electrically short-circuited state. For example, if the capacitive fuse is formed in a film thickness equal to that of a capacitive film of a DRAM cell, the potential difference required between the terminals when the capacitive film is broken down is about 7 V.
Although the case (1) and (2) are described, there may be sufficiently the possibility of needing two kinds of higher voltages in the single semiconductor device. In particular, the DRAM must inevitably be provided with the boosting circuit for the word line described in the case (1). The DRAM in the recent years is provided with the boosting circuits for cutting the fuses and the anti-fuses in order to relieve defective cells in many cases. However, conventionally, the boosting circuit is provided for each of the kinds of the higher voltages.
By the way, the lowering of the external power supply voltage VDD is generally advanced in the present semiconductor integrated circuit. Even in case of the DRAM, the power supply voltage is lowered from 3.3 V to 2.5 V, and then to 1.8 V. However, even if the power supply voltage VDD of the DRAM is lowered, the voltage necessary for the word line requires the same high voltage as in the conventional case. For this reason, when the power supply voltage VDD of 1.8 V is tried to be boosted up to the voltage of about 4 V, the boosting circuit is required which can boosts the voltage from the power supply voltage to two times or more of the power supply voltage.
As the boosting circuit for boosting the power supply voltage to two times or more of it, a boosting circuit 100 is conventionally known in which charge pump circuits are connected in series, as shown in FIG. 1. Such a conventional boosting circuit 100 of capacitance series connection type is described in Japanese Laid Open Patent Applications (JP-A-Heisei 11-328984 and JP-A-Heisei 7-264842). The conventional boosting circuit 100 contains a first boosting circuit 110 and a second boosting circuit 120. The first boosting circuit 110 is for applying a voltage higher than the power supply voltage VDD as an output voltage VPP1 to the word line as an internal circuit of the semiconductor device. The second boosting circuit 120 is for applying a voltage higher than the power supply voltage VDD as an output voltage VPP2 to a capacitive fuse as another internal circuit of the semiconductor device.
The first boosting circuit 110 includes an inverting element INV101, a first charge pump circuit, a second charge pump circuit, and switches SW101 and SW102. The first charge pump circuit has a capacitive section C101. The second charge pump circuit has a capacitive section C102. The inverting element INV101 is connected to a first side electrode of the capacitive section C101. One of terminals of the switch SW101 is connected to a second side electrode of the capacitive section C101. A first side electrode of the capacitive section C102 is connected to the other of the terminals of the switch SW101. One of terminals of the switch SW102 is connected to a second side electrode of the capacitive section C102. A node X1 is connected to the other of the terminals of the switch SW102. The word line is connected, as the internal circuit of the semiconductor device, to the node X1. When the switches SW101 and SW102 are turned off, the first side electrode of the capacitive section C101 is grounded in the first charge pump circuit, and the charge corresponding to the power supply VDD is accumulated in the capacitive section C101. In the second charge pump circuit, the first side electrode of the capacitive section C102 is grounded, and the charge corresponding to the power supply VDD is accumulated in the capacitive section C102.
The second boosting circuit 120 includes an inverting element INV102, a third charge pump circuit, a fourth charge pump circuit, a fifth charge pump circuit, and switches SW103 and SW104 and SW105. The third charge pump circuit has a capacitive section C103. The fourth charge pump circuit has a capacitive section C104. The fifth charge pump circuit has a capacitive section C105. The inverting element INV102 is connected to a first side electrode of the capacitive section C103. One of terminals of the switch SW103 is connected to a second side electrode of the capacitive section C103. A first side electrode of the capacitive section C104 is connected to the other of the terminals of the switch SW103. One of terminals of the switch SW104 is connected to a second side electrode of the capacitive section C104. A first side electrode of the capacitive section C105 is connected to the other of the terminals of the switch SW104. One of terminals of the switch SW105 is connected to a second side electrode of the capacitive section C105. A node X2 is connected to the other of the terminals of the switch SW105. One of terminals of the capacitive fuse or the anti-fuse is connected, as the internal circuit of the semiconductor device to the node X2. When the switches SW103, SW104 and SW105 are turned off, the first side electrode of the capacitive section C103 is grounded in the third charge pump circuit, and the charge corresponding to the power supply VDD is accumulated in the capacitive section C103. In the fourth charge pump circuit, the first side electrode of the capacitive section C104 is grounded, and the charge corresponding to the power supply VDD is accumulated in the capacitive section C104. In the fifth charge pump circuit, the first side electrode of the capacitive section C105 is grounded, and the charge corresponding to the power supply VDD is accumulated in the capacitive section C105.
As shown in FIG. 2, the first boosting circuit 110 is controlled such that the switches SW101 and SW102 are turned on at the same time that the output voltage VPP1 is applied to the word line as the internal circuit of the semiconductor device. When the switches SW101 and SW102 are turned on, a voltage (3*VDD) that is a voltage equal to three times of the power supply voltage VDD is applied to the node X1. That is, the voltage (3*VDD) is applied as the output voltage VPP1 to the word line.
As shown in FIG. 3, the second boosting circuit 120 is controlled such that the switches SW103, SW104 and SW105 are turned on at the same time that the output voltage VPP2 is applied to the capacitive fuse as the internal circuit of the semiconductor device. When the switches SW103, SW104 and SW105 are turned on, a voltage (4*VDD) that is a voltage equal to four times the power supply voltage VDD is applied to the node X2. That is, the voltage (4*VDD) is applied as the output voltage VPP2 to the capacitive fuse.
However, in the above conventional boosting circuit, there is a problem in the chip area of the boosting circuit 100 including the first boosting circuit 110 and the second boosting circuit 120. The charge pump circuit for carrying out the boosting operation typically uses an oxide film capacitor. However, the chip area of this capacitor is wide in the entire chip. For example, in a 512M DDR-DRAM designed in accordance with the 0.13 μm design rule, the chip area of the boosting circuit 100 exceeds 1% of the whole.
The boosting circuit 100 requires the first boosting circuit 110 and the second boosting circuit 120, if the different voltages higher than the power supply voltage are generated for circuit portions such as the word line or the capacitive fuse. For this reason, it requires the total of five charge pump circuits of two charge pump circuits in the first boosting circuit 110 and three charge pump circuits in the second boosting circuit 120. In this way, if the first and second boosting circuits 110 and 120 are required, the circuit area of the boosting circuit 100 becomes wide.
In conjunction with the above description, a negative voltage word line decoder is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 7-37396). In this conventional example, each of a plurality of drive circuits is connected to a word line, to drive it to a voltage which is not negative. Each of a plurality of negative charge pumps is connected with the word line to drive it to a negative voltage.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 8-162915). In this conventional example, a first capacitive section is connected to an input section. The first capacitive section is connected to a transfer gate which is connected to an output section. An external power source is connected between the transfer gate and the first capacitive section. A second capacitive section has one terminal connected to a gate section of the transfer gate and another terminal connected to the first capacitive section via a controller. A precharge section is connected to the gate section of the transfer gate to supply a voltage of the power source or a voltage of an internal power source to the gate section.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 10-214496). In this conventional example, a voltage clamp section clamps an output voltage to a first voltage lower than a single power source voltage by using a reference voltage. A boosting section boosts the clamped voltage to a positive or negative high voltage.
Also, a semiconductor boosting circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 10-304653). In this conventional example, the boosting circuit includes a plurality of pump blocks connected in series to generate a boosted voltage. A clock generator supplies a clock signal to each of the plurality of pump block. An output of at least one of the plurality of pump blocks is connected to a capacitive element via a diode.
Also, a semiconductor device is disclosed in Japanese Laid Open Patent application (JP-p2000-331489A). In this conventional example, a plurality of charge pump circuits are arranged in parallel and their output nodes are connected to a node in common. A clock generator supplies clock signals of different phases to the plurality of charge pump circuits such that they carries out boosting operations in synchronism with the clock signals, respectively. A control circuit controls the clock generator based on the boosted voltage.
Also, a semiconductor boosting circuit is disclosed in Japanese Pant no. 3012634. In this conventional example, in a boosting control section, a boosting section amplifies an output of an oscillation circuit by a logic section of a predetermined number of inverters, boosts an output of the logic section via a first pumping capacitor, supplies the boosted output to a first output transistor for outputting it to a load circuit as a first control voltage. A voltage conversion boosting section amplifies the output of the oscillation circuit by a logic section of a predetermined number of inverters, boosts an output of the logic section via a second pumping capacitor, supplies the boosted output to a second output transistor for outputting as a second control voltage. A voltage conversion circuit converts the output of the oscillation circuit into a drive power source voltage level by using the second control voltage as a drive power source voltage, and supplies the converted output to the first and second output transistors.